1. Field of the Invention
Embodiments of the invention relate generally to semiconductor chips. More particularly, embodiments of the invention relate to an electrostatic discharge circuit capable of protecting internal circuits of the semiconductor chips from static electricity and methods of reducing an input capacitance of the semiconductor chips.
A claim of priority is made to Korean Patent Application No. 10-2006-0045614, filed on May 22, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
The ability to withstand high voltage static electricity can have a significant impact on the reliability of semiconductor devices. For example, unless a semiconductor device is designed to withstand static electricity, the semiconductor device can be destroyed by incidental contact with charged objects in the device's environment. The sensitivity of a semiconductor device to the effects of static electricity becomes exacerbated as the size of features in the semiconductor device grow smaller, i.e., as the level of integration in the device increases.
Interactions between a semiconductor device and static electricity can be conceptualized as a momentary flow of current between the device and a statically charged object in the device's environment. The current flow typically results from contact with the charged object. Where current from static electricity flows into internal circuits of the semiconductor device designed to operate at relatively low voltages, the internal circuits can be fatally damaged. To prevent such damage from occurring, semiconductor devices often include a static electricity current path allowing current from static electricity to flow without damaging internal circuits of the devices. Preferably, the current path is capable of discharging a large amount of electrical charge in a short period of time.
The static electricity current path is often implemented by a protection circuit installed between an external signal input pad connected to an external pin of the semiconductor device and an internal circuit. The external pin is typically located so as to readily come in contact with static electricity. Another name for the protection circuit is an electrostatic discharge (ESD) circuit. As an example of the ESD circuit's operation, where static electricity is applied to the ESD circuit, the static electricity passes through the ESD circuit, and therefore internal circuits of the semiconductor device are protected against the static electricity. In addition to protecting the semiconductor device against fatal damage to internal circuits, the ESD circuit is preferably designed to further protect the reliability of the device's operation against the effects of static electricity.
As an example, ESD circuits are desirable for protecting internal circuits and operation of dynamic random access memory (DRAM) devices. The problem of protecting DRAM devices against static electricity becomes increasingly important as the size of the DRAM devices continues to decrease.
Certain environments provide somewhat predictable amounts of static electricity to semiconductor devices such as DRAM devices. For example, when a semiconductor device is manufactured, the device may be passed through a handler lane used for testing products after package assembly. The handler lane may impart static electricity to the device with a low voltage of about 250V, however, the static electricity can be discharged from the handler lane with low impedance. Static electricity discharged in this way can be said to be discharged in a “machine mode.”
Another way in which static electricity may be discharged to a semiconductor device is in a “human body mode.” In the human body mode, static electricity is discharged from the human body to a semiconductor device when a human user touches a body part to the semiconductor device. Static electricity discharged from a human body to a device typically has a high voltage of about 2000V and is discharged through great impedance.
In order to protect internal circuits of a semiconductor device from being damaged by an inflow of current from static electricity, various protection circuits may be installed in a semiconductor device. One of the protection circuits may be an ESD circuit disposed between an input pad and an input buffer.
FIG. 1 is a circuit diagram of a conventional ESD circuit for a semiconductor device. Referring to FIG. 1, a conventional ESD circuit 10 is connected between an input pad PAD of the semiconductor device and an input buffer 12.
Signals are applied to input pad PAD from an external source outside the semiconductor device. For example, the signals may be applied to input pad PAD through an external pin of a semiconductor package, or before the semiconductor device is packaged, through a tester pin via a prober tip.
Input buffer 12 buffers an external signal applied through input pad PAD, and outputs a buffered signal IN to a next terminal (not shown) of input buffer 12. An input terminal of input buffer 12 is connected to a node N1 and an output terminal of input buffer 12 is connected to a node N2.
ESD circuit 10 is connected between input pad PAD and input buffer 12, to protect input buffer 12 from static electricity. ESD circuit 10 includes two diodes D1 and D2. Diode D1 comprises a positive metal-oxide semiconductor (PMOS) transistor and diode D2 comprises a negative metal-oxide semiconductor (NMOS) transistor.
The PMOS transistor in ESD circuit 10 has a first terminal connected to node N1, a second terminal connected to a power terminal VDD, and a gate connected to the source of the PMOS transistor in ESD circuit 10. In other words, where static electricity is not applied to ESD circuit 10, diode D1 is connected in a reverse bias configuration.
The NMOS transistor in ESD circuit 10 has a first terminal connected to node N1, a second terminal connected to ground VSS, and a gate connected to the second terminal of the NMOS transistor in ESD circuit 10. In other words, where static electricity is not applied to ESD circuit 10, diode D2 is connected in a reverse bias configuration.
Where static electricity having a voltage level higher than power source voltage VDD is applied to input pad PAD, the static electricity is discharged through diode D1. On the other hand, where static electricity having a voltage level lower than ground VSS is applied to input pad PAD, static electricity is discharged through diode D2.
Thus, where static electricity having a higher voltage level than power source voltage VDD is applied to input pad PAD, or where static electricity having a lower voltage level than ground VSS is applied to input pad PAD, ESD circuit 10 discharges a large amount of charge. As a result, input buffer 12 is prevented from being damaged. In general, the static electricity tends to have a voltage level that is significantly higher or lower than power source voltage VDD or ground VSS, respectively.
FIG. 2 is a sectional view schematically illustrating a vertical structure of diode D2 shown in FIG. 1 and FIG. 3 is a sectional view schematically illustrating a vertical structure of diode D1 shown in FIG. 1.
Referring to FIG. 2, diode D2 comprises an NMOS transistor including a gate 24, a source 26, and a drain 27. Gate 24 and source 26 are both connected to ground VSS and drain 27 is connected to a drain voltage Vdrain. In addition, the NMOS transistor includes a p-type body 22 also connected to ground VSS. Each of source 26 and drain 27 are formed by a well comprising a region into which n-type impurities of a high density are implanted. A region 28 is also formed in body 22 by implanting p-type impurities with a high density into body 22. A junction diode JD1 is positioned between body 22 and source 26 of the NMOS transistor and a junction diode JD2 is positioned between body 22 and drain 27 of the NMOS transistor. Although a gate oxide is typically included in the NMOS transistor, no gate oxide is explicitly shown in order to simplify the drawings.
The voltage applied to body 22 prevents a PN junction from forming between circuit elements in a partial forward bias in a semiconductor chip, and further prevents data loss or latch-up in memory cells. The voltage applied to body 22 also reduces a change of threshold voltage of the NMOS transistor based on a back-gate effect to obtain a stable operation of the device and improve the device's operating speed. In general, the voltage applied to the body, or bulk, of a transistor may be referred to as a bulk bias voltage.
In diode D2 having the structure illustrated in FIG. 2, where static electricity is applied to input pad PAD (FIG. 1) and therefore drain voltage Vdrain is applied to node N1 (FIG. 1) with a voltage level less than ground VSS, charges are discharged through diode D2. Meanwhile, where static electricity is not applied to input pad PAD (FIG. 1), diode D2 is reverse biased and therefore it has a significant junction capacitance. More particularly, in a normal case, junction diode JD2 between body 22 and drain 27 is reverse biased and therefore diode D2 has a significant junction capacitance. At the same time, junction diode JD1 between body 22 and source 26 is also reverse biased, and therefore has a junction capacitance. However, junction diode JD1 is reverse biased to a smaller degree than junction diode JD2.
Referring to FIG. 3, diode D3 comprises a PMOS transistor including a gate 34, a source 36, and a drain 37. Gate 34 and source 36 are both connected to power source voltage VDD and drain 37 is connected to drain voltage Vdrain. In addition, the PMOS transistor includes a n-type body 32 also connected to power source voltage VDD. Each of source 36 and drain 37 are formed by a well comprising a region into which p-type impurities of a high density are implanted. A region 38 is also formed in body 32 by implanting n-type impurities with a high density into body 32. A junction diode JD3 is positioned between body 32 and source 36 of the PMOS transistor and a junction diode JD4 is positioned between body 32 and drain 37 of the PMOS transistor. Although a gate oxide is typically included in the PMOS transistor, no gate oxide is explicitly shown in order to simplify the drawings.
In diode D1 having the structure illustrated in FIG. 3, where static electricity is applied to input pad PAD (FIG. 1) and therefore drain voltage Vdrain is applied to node N1 (FIG. 1) with a voltage greater than power source voltage VDD, charges are discharged through diode D1. Meanwhile, where static electricity is not applied to input pad PAD (FIG. 1), diode D1 is reverse biased and therefore it has a significant junction capacitance. More particularly, in a normal case, junction diode JD4 between body 32 and drain 37 is reverse biased and therefore diode D1 has a significant junction capacitance. At the same time, junction diode JD4 between body 32 and source 36 is also reverse biased, and therefore has a junction capacitance. However, junction diode JD3 is reverse biased to a smaller degree than junction diode JD4.
In diode D1 having the above-mentioned structure, where static electricity is applied to input pad PAD (FIG. 1) and a drain voltage Vdrain as a node (N1 of FIG. 1) voltage is greater than power source voltage VDD, a charge is discharged through diode D1. Meanwhile, in a normal case where static electricity is not applied to input pad PAD (FIG. 1), diode D1 is reverse biased and has a junction capacitance. That is, in the normal case, junction diode JD4 between body 32 and drain 37 is reverse biased, and therefore diode D1 has a junction capacitance. In addition, a junction capacitance exists between body 32 and source 36.
A semiconductor chip having an ESD circuit such as that illustrated in FIGS. 1-3 has junction capacitances as described above where a relatively small amount of static electricity flows into the semiconductor chip.
The magnitude of input capacitance in the conventional semiconductor devices depends on various factors such as the junction capacitances in the electrostatic discharge circuit. As the performance and capacity of the devices increases, the input capacitance of the devices tends to increase accordingly. For instance, leading edge semiconductor devices often include stack packages in order to increase the performance of the devices. However, using such stack packages tends to increase the overall input capacitance of the devices.
Increasing the input capacitance of semiconductor devices tends to decrease the setup margin of the devices, causing defects in their operation or otherwise degrading their performance. Certain sources of input capacitance cannot be readily modified to reduce the input capacitance. For example, components necessary for proper operation of the chips, such as drivers, cannot be readily modified to reduce the input capacitance in order to overcome the lack of setup margin.
The ability of a memory module to drive a semiconductor device depends on the input capacitance of the semiconductor device. More particularly, the number of semiconductor chips that can be driven by each output pin of a driver of the memory module is limited by the input capacitance of the semiconductor chips. A wide variety of memory module types exist, such as Dual Inline Memory Modules (DIMMs), Unbuffered DIMM (UDIMM), Small Outline DIMM (SODIMM), Registered DIMM (RDIMM), and Fully Buffered DIMM (FBDIMM), to name but a few. In these memory modules, the input capacitance of semiconductor chips tends to limit the number of semiconductor chips per output pin of a main board controller chip for the UDIMM and the SODIMM, the number of semiconductor chips per output pin of a register for the RDIMM, and the number of semiconductor chips per output pin of an Advanced Memory Buffer (AMB) for the FBDIMM.
Accordingly, decreasing the input capacitance of semiconductor chips may increase the number of semiconductor chips that can be driven by each output pin of a memory module driver and enhance the performance of the memory module and the semiconductor chip.